For example, “A 550 Mb/s GMR Read/Write Amplifier using 0.5 μm 5 V CMOS Process” by Steven Lam et al. and p. 358 to 359 of “2000 IEEE International Solid-State Circuits Conference Digest of Technical Papers” (Non-patent document 1) disclose a circuit for writing data by driving a magnetic head in a magnetic storage device such as a hard disk drive.
The non-patent document 1 discloses a write circuit composed of an H-bridge circuit, and data is written through two-stage MOS transistors connected in series in the write operation in this write circuit. More specifically, one of the two-stage MOS transistors has a function to set write current and the other thereof has a function as a switch. Then, when the switch is turned on, write current is supplied to a magnetic head to write data.
In addition, an output circuit and a driver circuit are disclosed in, for example, Japanese Patent Application Laid-Open No. 5-152926, U.S. Pat. No. 6,222,780, Japanese Patent Application Laid-Open No. 8-107344, and U.S. Pat. No. 2002/0140458.
Japanese Patent Application Laid-Open No. 5-152926 discloses an output circuit in which output impedance can be varied in an analog manner. In the configuration of the output circuit, an inverter circuit located in a previous stage of a MOS transistor provided in an output stage is provided with a function to vary the power supply voltage of the inverter circuit. As a result, since the input potential of the MOS transistor in an output stage can be varied, it is possible to control the output impedance. Therefore, malfunction due to the impedance mismatch can be prevented.
U.S. Pat. No. 6,222,780 discloses a semiconductor static memory in which cell ratio difference caused by manufacturing variance can be corrected. In the configuration of the semiconductor static memory, a function to vary the power supply voltage of a word line driver is provided. Therefore, the cell ratio difference can be corrected by adjusting the potential of the word line to an appropriate value, and thus, the stable write operation and data holding operation can be realized.
In addition, Japanese Patent Application Laid-Open No. 8-107344 discloses a CMOS output circuit in which means for preventing that a P channel MOS transistor and an N channel MOS transistor are simultaneously turned on is provided so as to prevent the generation of through current. U.S. Pat. No. 2002/0140458 discloses a CMOS inverter circuit in which appropriate bias voltage in accordance with the threshold voltage of a gate terminal of a MOS transistor provided in an output stage and an input signal via an AC coupling are applied to the gate terminal of the MOS transistor so as to reduce the influence of the threshold voltage under the low voltage operation.